Riccardo Fontanini

I'm an electronic engineer graduated at University of Udine. Now I'm attending the 2nd level (Master degree) course of electronic engineering.
I also worked on IoT solutions and designed Cloud based system. I have been collaborating with Microsoft as Microsoft Student Partner since 2016.
This site aims to collect projects that I worked on. You can use all material on this site, you can also write me on social: Facebook and Linkedin. Also you can follow me on Github

Projects

Development of AES Processor (128, 192, 256 bit) Multicore on FPGA

Implementation of AES encryption standard 128, 192 and 256 bits, with dynamic Sbox, based on AES paper, "A Highly Regular and Scalable AES Hardware Architecture" article of Stefan Mangard and "An ASIC Implementation of the AES SBoxes" article of Johannes Wolkerstorfer, Elisabeth Oswald, and Mario Lamberger. This Project has been modified to implement ciphers' parallelism and some improvements to speed up encryption and decryption.

Computer Security - Backdoor hardware software

Project of computer security based on Backdoors software and hardware.

Exercises on FPGA

Some exercises to improve my skills on FPGA programming (VHDL). I used Atlys Spartan-6 FPGA ( Xilinx Spartan-6 LX45 )

Data analysis on books

Elaboration, classification and data analysis on books. I used most common data analysis tools of python's environment. After cleaning and visualizing data I worked on classification of books. Very impotant thing is the suggestion engine based on random forest algorithm.

CUDA elaboration

Elaboration data on GPUs (language C) is one of the most important way to speedup algorithms, data analysis, neural networks and cellular automata. CUDA is a parallel computing platform and programming model developed by NVIDIA for general computing on graphical processing units (GPUs). With CUDA, developers are able to dramatically speed up computing applications by harnessing the power of GPUs.

MIPS implementation in VHDL

MIPS (Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by MIPS Technologies . This is an implementation in VHDL.

Thesis project - SISTEMA DI INTERFACCIAMENTO BASATO SU BOT PER APPLICAZIONI STRUTTURATE A MICROSERVIZI

This is my first thesis project SISTEMA DI INTERFACCIAMENTO BASATO SU BOT PER APPLICAZIONI STRUTTURATE A MICROSERVIZI means (interfacing system based on BOT for microservices based applications). It's a interface that allow you to run all kind of programs on a system and interact with them through a BOT, that interfaces on common social networks like Facebook, Twitter, Telegram and so on... Is based on Microsoft Bot Framework.